1. Field of the Invention
This invention relates generally to integrated circuits and, more particularly, to a ball grid array in which one or more vias are formed through a substrate to electrically interconnect electrically conductive traces formed on a surface of the substrate to solder ball pads formed on another surface of the substrate.
2. Related Art
A ball grid array is a type of packaged integrated circuit in which one or more integrated circuit chips (semiconductor dice on which electrically conductive circuitry are formed) are mounted on a surface (top substrate surface) of a substrate, and electrical connection to electrically conductive material not part of the packaged integrated circuit, such as a printed circuit board, is made by an array of solder balls located on a surface of the substrate opposite the surface to which the integrated circuit chip or chips are attached (bottom substrate surface). Passive components such as resistors or capacitors can also be mounted on the top surface of the substrate. The substrate can be a multi-layer substrate, electrically conductive traces and/or regions being formed on a surface of each layer of the substrate, such as described in U.S. Pat. No. 4,975,761 to Chu. The integrated circuit chip or chips and the passive components are typically encapsulated by, for instance, plastic to protect the integrated circuit chip or chips and the passive components from the external environment. The integrated circuit chip or chips are electrically connected to the substrate by wirebonding, tape-automated bonding (TAB), or flip-chip interconnection. Ball grid arrays allow a high density of external chip connections to be made as compared to other packaged integrated circuits having leads extending from the package.
FIG. 1 is a cross-sectional view of a prior art ball grid array 100. An integrated circuit chip 101 is attached to a substrate 102. Electrically conductive bond wires 106 make electrical connection between selected ones of bond pads (not shown) formed on the chip 101 and electrically conductive traces 105 formed on the top surface 102a of the substrate 102. Encapsulant 103 is formed on the top surface of the substrate 102 to cover the chip 101, bond wires 106 and a portion of the traces 105. The traces 105 extend beyond the encapsulant 103 to through-holes 107 that are formed through substrate 102 to the bottom surface 102b of the substrate 102. The through-holes 107 are plated with electrically conductive material. Electrically conductive traces 109 formed on the bottom surface of the substrate 102 extend from the through-holes 107 to pads 108 on which solder balls 104 are formed.
In the conventional ball grid array 100, electrical connection between the top surface 102a and the bottom surface 102b of the substrate 102 is made by through-holes 103. To prevent the encapsulant 107 from flowing out from through-holes 107 during application of encapsulant 103, the through-holes 107 are located outside the region in which encapsulant 103 is formed.
Potential problems have been found in manufacturing ball grid arrays. First, because the through-holes 107 are located outside the encapsulant area, the substrate 102, and, thus, the ball grid array 100, cannot be made as small as desired. Second, the presence of the traces 105 on the top surface 102a creates a rough surface so that during the encapsulation process, a mold surface contacting top surface 102a is not flush with respect to the entire surface 102a, thus allowing encapsulant bleed or flash to form on surface 102a. Further, a good seal does not form at the interface between the traces 105 and the encapsulant 103 so that moisture and contaminants can enter the die area along this interface.
In some prior ball grid arrays, solder resist has been added over the surface 102a (including over the traces 105) to smooth the surface 102a and improve the seal between the encapsulant 103 and traces 105 in order to improve the above problems. However, this has caused other problems such as poor heat resistance and higher cost, and has not totally solved the encapsulant bleed/flash and moisture problems.
Additional problems have been encountered with the ball grid array 100. Since the through-holes 107 penetrate entirely through the substrate 102, the length of the through-holes 107 is large. This large length causes high stress in the plating formed in the through-holes 107, especially on the corners formed where the through-holes adjoin the top and bottom surfaces 102a and 102b, respectively.
Previously, through-holes 107 have been formed by mechanical drilling. When through-holes 107 are formed by mechanical drilling, the diameter of through-holes 107 cannot be made smaller than a certain size because of limitations on the size of the drill bits used to form the through-holes 107. As the drill bits get smaller, they are increasingly prone to breakage during drilling, making mechanical drilling impractical as a means to form through-holes 107 with very small diameters. Further, in mechanical drilling of through-holes 107, a minimum spacing between through-holes 107 must be maintained. If the spacing is too small, the material lying between an existing through-hole 107 and a through-hole 107 being drilled will deform due to the forces imparted by the drill bit. Thus, the density of through-holes 107 (and, thus, electrical interconnections within the substrate 102) is limited when the through-holes are formed by mechanical drilling. Additionally, the speed of through-hole 107 formation is limited when mechanical drilling is used since through-holes 107 can only be drilled one at a time.